Sunday, July 17, 2005

Teaser--the first view of the CPU

After much preparation, I've finally started to assemble the CPU. Sorry for the teaser, but this diagram is 1) completely nonfunctional; it'd just start dropping balls on the floor shortly after starting up, and 2) not an imagemap. Given that it doesn't work anyway, and most of its components are already documented, I didn't bother setting up all the links for each of the subcomponent definitions.

What I've done here is mainly just plunk down the components I've designed so far and make the obvious connections between them. The less-obvious connections, which is to say those which will vary based on the particular instruction, are still missing. As I put in the instruction decode logic, I'll be able to add and test a few instructions at a time until the CPU is complete.

As I bolt things together, I've been finding small changes that need to be made in some of the components. In some cases it's as simple as deleting functionality that's going to be taken care of more efficiently elsewhere, but generally it's just rearranging ports such that more internal information is exposed to the enclosing scope. Many of the components toss all setup balls out a single "junk" output when they're done with them, which throws away such information as "what values were input?" and "was that the last of the setup balls?". These turn out to be quite handy for the controlling state machines, who then don't need to waste time and gates maintaining the same data themselves.

Incidentally, I expect that I'll do the branch and jump instructions first [unconditional first, then the conditional ones], as it's pretty hard to test a CPU if it doesn't have a working program counter, and the PC design is fairly closely tied to the branch and jump logic.


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