Tuesday, October 04, 2005

Back on the horse

What with my vacation, far too many weddings, work, and general busyness, I haven't managed a single post in just over 2 months. Nor have I managed to do any work and just not post about it. However, that's all over now...for a bit.

Sunday night I got back to work on the cpu design, and am now able to report great progress. Why? Because I was clever enough not to test what I had designed! Had I in fact run a simulation, I would have found that none of it worked, stayed up until all hours trying to fix it, and perhaps ended the night dissatisfied and with it all still broken. Not having done any testing, I can report that I've made lots of progress, and that it merely needs a bit of debugging. Isn't that great?

Anyway, what I got in on Sunday is the rest of the ALU operation state machines. That means absolutely everything needed in order to execute any type of ADD, SUB, AND, OR, or XOR instruction [immediate or register arguments, carry-in from CCR or not, writeback to a register, CCR bits CVZS set as appropriate afterwards, increment the PC and turn off the stove when you're done]. Whee! Actual instructions, and they might even work!

Anyway, here is an image of the top-level design, shrunk down to the point where you really can't see anything. For those of you with more time on your hands, here is a much bigger image of same, blown up to the point where you can just about read my notes if you squint.

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