Sunday, October 23, 2005

First light!

Two weeks ago, on the evening of Friday, October seventh, the Ball Computer executed its first full instruction [an "addi"]. Whee! That includes reading the program counter, fetching the instruction from ROM, reading a value from a register, adding a constant to it, dealing with the CCR, doing the register writeback, incrementing the PC, and getting ready to run the next instruction.

I was quite pleased to find that it only took a few hours of debugging to get it working, and that the errors were pretty minor: one place where I'd swapped bit 12 and 14 of the opcode, and a number of connections that I'd just forgotten to hook up [all but one of them just the ball return for junk outputs].

I'm now taking a break from debugging ALU ops in order to improve visibility into values within bcd. This should make it much faster and easier to debug the rest of the opcodes.

Incidentally, the instruction took a whopping 1600 gate delays [and therefore 1600 wire delays] to execute. If each of those delays is on the order of 0.5 seconds in real hardware, we're talking about 25 minutes per instruction! However, I'm pretty sure I can improve on that by a factor of 10 with fast gates and the parallelization of processing that I've got planned for version 2.0 of the CPU.

Tuesday, October 04, 2005

Back on the horse

What with my vacation, far too many weddings, work, and general busyness, I haven't managed a single post in just over 2 months. Nor have I managed to do any work and just not post about it. However, that's all over now...for a bit.

Sunday night I got back to work on the cpu design, and am now able to report great progress. Why? Because I was clever enough not to test what I had designed! Had I in fact run a simulation, I would have found that none of it worked, stayed up until all hours trying to fix it, and perhaps ended the night dissatisfied and with it all still broken. Not having done any testing, I can report that I've made lots of progress, and that it merely needs a bit of debugging. Isn't that great?

Anyway, what I got in on Sunday is the rest of the ALU operation state machines. That means absolutely everything needed in order to execute any type of ADD, SUB, AND, OR, or XOR instruction [immediate or register arguments, carry-in from CCR or not, writeback to a register, CCR bits CVZS set as appropriate afterwards, increment the PC and turn off the stove when you're done]. Whee! Actual instructions, and they might even work!

Anyway, here is an image of the top-level design, shrunk down to the point where you really can't see anything. For those of you with more time on your hands, here is a much bigger image of same, blown up to the point where you can just about read my notes if you squint.